The present invention relates generally to complementary metal oxide semiconductor (CMOS) random access memory (RAM) applications, and more particularly, relates to a method and apparatus for tri-state dynamic body charge modulation for sensing devices in silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) random access memory (RAM) applications.
Silicon-on-insulator (SOI) technology is an enhanced silicon technology currently being utilized to increase the performance of digital logic circuits. By utilizing SOI technology, designers can increase the speed of digital logic integrated circuits or can reduce their overall power consumption. These advances in technology will lead to the development of more complex and faster computer integrated circuits that operate with less power.
SOI semiconductors include a thin layer of silicon placed on top of an insulator, such as silicon dioxide (SiO2) or glass, and a MOS transistor built on top of this structure. The main advantage of constructing the MOS transistor on top of an insulator layer is to reduce the internal capacitance of the transistor. This is accomplished by placing the insulator oxide layer between the silicon substrate and the impurities required for the device to operate as a transistor. Reducing the internal capacitance of the transistor increases its operating speed. With SOI technology, faster MOS transistors can be manufactured resulting in faster electronic devices.
Dynamic and dual rail silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) circuits are prone to performance variation and mismatch in transfer characteristics due to body potential and threshold voltage differentials. This is a direct result of circuit operating history and dissimilar time constants to charge and discharge field effect transistor (FET) bodies as compared with the actual access times or cycle times. Repetitive read operations performed on a sense amplifier over time can result in significant body potential bias, and consequently mismatches in FET threshold voltage and amplifier transfer characteristics. This degrades the circuit noise margin, reduces the differential gain and switching sensitivity of the amplifier, lowers performance, and can potentially cause logic faults.
Various arrangements are known for silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technologies.
SOI DRAM circuit arrangements are disclosed by S. Kuge et al. in a publication entitled xe2x80x9cSOI-DRAM Circuit Technologies For Low Power High Speed Multi-giga Scale Memoriesxe2x80x9d, Digest Tech. Papers, Symposium on VLSI Circuits, 1995, pp. 103-104. A synchronous technique of body-bias control is described for SOI devices. A problem with the disclosed sense amplifier arrangement is that the sense amplifier may be jammed or temporarily inhibited during active switching.
U.S. patent application Ser. No. 09/498,387 filed Feb. 3, 2000, by Allen et al. and entitled xe2x80x9cSOI CMOS SENSE AMPLIFIER WITH ENHANCED MATCHING CHARACTERISTICS AND SENSE POINT TOLERANCExe2x80x9d discloses a silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) sense amplifier with improved matching characteristics and sense point tolerance under no penalty of performance degradation. The sense amplifier includes a silicon-on-insulator (SOI) field effect transistor. A flooding field effect transistor is coupled to a body of the silicon-on-insulator (SOI) field effect transistor. The flooding field effect transistor is activated before the sense amplifier is set. The flooding field effect transistor has an opposite polarity of the silicon-on-insulator (SOI) field effect transistor. The flooding field effect transistor provides a charging path to a voltage supply rail. A pair of flooding field effect transistors serve as charging to voltage supply rail elements for silicon-on-insulator (SOI) field effect transistors on each side of complementary bitline structures of the sense amplifier. The flooding field effect transistor is substantially smaller than the silicon-on-insulator (SOI) field effect transistor. While this patent application discloses improvements over other known arrangements, substantial leakage current may exist at stand-by.
A need exists for improved complementary metal oxide semiconductor (CMOS) sense amplifiers in silicon-on-insulator (SOI) technologies. It is desirable to provide a method and apparatus for tri-state dynamic body charge modulation for sensing devices in silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) applications, such as random access memory (RAM) applications. It is desirable to provide such method and apparatus that enables high performance operation, good matching characteristics, and low stand-by leakage suitable for low-power RAM applications.
A principal object of the present invention is to provide a method and apparatus for tri-state dynamic body charge modulation for sensing devices in silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) applications, such as random access memory (RAM) applications. Other important objects of the present invention are to provide such method and apparatus for tri-state dynamic body charge modulation for sensing devices in silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) applications substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, a method and apparatus are provided for tri-state dynamic body charge modulation for sensing devices in silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) applications. A sense amplifier includes a silicon-on-insulator (SOI) field effect transistor. A tri-state body charge modulation circuit is coupled to a body of the silicon-on-insulator (SOI) field effect transistor. The body charge modulation circuit provides a high body bias preparatory state; a floating body state and a low body bias stand-by state.
In accordance with features of the invention, the tri-state body charge modulation circuit includes a P-channel field effect transistor (PFET) and an N-channel field effect transistor (NFET) connected in series between a high voltage potential and a low voltage potential. The junction of the series connected PFET and NFET is coupled to the SOI FET body for providing a high impedance state, a charging path to a high voltage potential and a discharging path to a low voltage potential. The tri-state body charge modulation circuit includes a NAND gate and a NOR gate providing a high body voltage signal and a low body voltage signal. The high body voltage signal output of the NAND gate is applied to the gate of PFET. The low body voltage signal output of the NOR gate is applied to the gate of NFET.